1. Field
Disclosed embodiments relate to semiconductor microelectronic packages and methods of formation.
2. Discussion of Related Art
Today's consumer electronics market frequently demands complex functions requiring very intricate circuitry. Scaling to smaller and smaller fundamental building blocks, e.g. transistors, has enabled the incorporation of even more intricate circuitry on a single die with each progressive generation. On the other hand, although scaling is typically viewed as a reduction in size, multiples of packaged die are increasingly coupled together for advanced functionality and horse-power in a computing system. Also, the size of a particular semiconductor package may in fact be increased in order to include multiple die within a single semiconductor package.
However, structural issues may arise when attempting to couple multiples of packaged die. For example, the effect of differences in the coefficients of thermal expansion (CTE) between components used in the semiconductor packages can lead to detrimental defects when adding packaged die together. Similarly, the effect of differences in the coefficients of thermal expansion (CTE) between components used within a single semiconductor package can lead to detrimental defects as a result of performing a semiconductor die packaging process for more than one die within the single package.
Semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support larger circuit density. For example, some semiconductor packages now use a coreless substrate, which does not include the thick resin core layer commonly found in conventional substrates. Furthermore, the demand for higher performance devices results in a need for an improved semiconductor package that enables mixed technology die stacking or provide package stacking capability while maintaining a thin packaging profile and low overall warpage to be compatible with subsequent assembly process.